1. Field of the Invention
The present invention relates to a low defect density, substantially crack-free (Ga,Al,In)N material, useful for fabrication of Group III-V nitride devices, and also relates to a hydride vapor phase epitaxy (HVPE) process for making such low defect density, substantially crack-free (Ga,Al,In)N material.
2. Description of the Related Art
(Ga,Al,In)N materials have long been considered for potential device applications, including UV-to-green light emitting diodes, lasers and detectors, as well as various other high temperature, high power, and/or high frequency electronic devices. The appeal of (Ga,Al,In)N materials for such applications is that the band gap of such material can be adjusted by correspondingly varying the composition, to yield band gap values in the range of from 1.9 to 6.2 electron volts (eV).
The potential of GaN and related materials associated with such wide energy bandgap enables a myriad of devices ranging from ultraviolet laser diodes to solar blind detectors. The key to realizing this potential is fabricating high quality material. The use of high quality lattice-matched native nitride substates would be an ideal template on which to fabricate such high quality material. Unfortunately, a suitable, high quality lattice-matched substrate for (Ga,Al,In)N does not exist. As a result, poor lattice-match materials such as sapphire have been used as a substrate in prior art attempts to grow suitable (Ga,Al,In)N layers for device fabrication. Due to the lattice mismatch, the (Ga,Al,In)N layers grown on sapphire or related materials are characterized by a large defect density. The art has proposed the use of buffer layers to compensate for the lattice-mismatch, but such approach has not been satisfactory in yielding useful base structures for device fabrication.
The majority of the defects in heteroepitaxially grown GaN are threading dislocations (TDs) which are associated with the misfit between the GaN and substrate. GaN grown on sapphire, silicon carbide or other similarly poorly lattice-matched substrate, typically contains greater than 108 dislocations per cm2 of surface. The dislocations form to accommodate the difference in lattice constant between the substrate and GaN material grown on the substrate. Defects/dislocations generated in the initial layer propagate to the active region of the device. In addition, similar dislocations, although lower in density, occur because of lattice constant differences between the individual layers of the device.
Although dislocations have long been known to be a serious problem for conventional Group III-V devices, only recently has there been direct evidence that dislocations are associated with undesirable materials characteristics and device problems in the III-V nitride system. A correlation exists between mixed character threading dislocations and non-radiative recombination centers and when the density of dislocations is greater than xcx9c109 cmxe2x88x922, negatively charged dislocations can be the dominant scattering source in GaN.
Further, compositional and growth rate inhomogeneities, including V-defects, originate at the site of threading dislocations and, as may be shown by Electron Beam Induced Current (EBIC) investigation, dislocations may also serve as a path for Mg migration.
As an example of such defect-impacted performance character, for a (Ga,Al,In)N-based ultraviolet laser diode as an illustrative device structure, more than 2 orders of magnitude increase in the lifetime of the ultraviolet laser diode may be achieved by suitable formation of the GaN film material with a substantially reduced density of defects in the material.
Thus, the large lattice constant and thermal coefficient of expansion (TCE) mismatch between the epitaxial films and foreign substrates results in a high density of optically and electrically active defects which limit device performance and lifetimes. There is therefore a compelling need to lower the defect density in (Ga,Al,In)N materials.
With respect to the (Ga, Al, In)N material of the present invention as hereinafter described, the art generally has taught away from the process conditions for growth of (Ga, Al, In)nitride materials that are employed in the practice of the present invention. The art has, therefore, not achieved a dislocation density less than 107 cmxe2x88x922 for crack-free areas larger than 1 cm2. A summary of the relevant teachings of the art is therefore set out below, by which the advance and achievement of the present invention may be better appreciated.
Perkins et al. (N. R. Perkins, M. N. Horton, Z. Z. Bandic, T. C. McGill, and T. F. Kuech, Mat. Res. Soc. Symp. Proc. 395 (1996) 243) describes the effect of growth temperature on the crystallinity of a GaN film produced by HVPE and the use of growth temperatures in the range of 1030xc2x0 C. to 1050xc2x0 C. Such growth conditions are disclosed to minimize the full width half maximum (FWHM) of double crystal x-ray diffraction peaks over the temperature range of 850xc2x0 C. to 1100xc2x0 C. At the same time, the width of the photoluminescence excitation was not improved by using lower temperatures in this study. Perkins et al. recognized that xe2x80x9cunder non-optimum growth conditions, occasional pits are noted along the surface . . . [that] vary in size and distribution,xe2x80x9d and they observed cracking in films that were greater than 20 xcexcm in thickness.
Molnar et al. (R. J. Molnar, W. Gotz, L. T. Romano, N. M. Johnson, J. Cryst. Growth, 178 (1997) 147.) disclose that higher growth temperature and slower growth rates flattened out hexagonal islands, (i.e., produce smoother surface morphology).
Hwang et al. (J. S. Hwang, A. V. Kuznetsov, S. S. Lee, H. S. Kim, J. G. Choi, and P. J. Chong, J. Cryst. Growth, 142 (1994) 5) describe surface morphology improvements with increased growth temperature.
Nickl, et al. (J. J. Nickl, W. Just, and R. Bertinger, Mat. Res. Bull. 9 (1974) 1413) disclose that a growth temperature of 1030xc2x0 C. optimized the ratio of near band edge photoluminescence emission (by a greater extent in the case of higher quality films) to deep level emission at xcx9c2.2 eV.
Melnik et al., (Y. V. Melnik et al., MRS Internet Journal, 2 (1997) article 39) grew GaN on SiC substrates and etched away the SiC by reactive ion etching. The GaN dimensions were at most 7 mm per side, limited by TCE-related cracking.
Poroswski, et al. (S. Poroswski, et al., Mat. Res. Soc. Symp. Proc. 449 (1997) 35) report free-standing GaN as large as 0.7 cm2 by high pressure sublimation.
Usui, et al. (A. Usui, et al., Jpn. J. Appl. Phys. 36 (1997) 899) describe low defect density thick HVPE GaN epitaxial growth producing a defect density of 6xc3x97107 defects/cm2 at growth rates of up to 100 microns per hour. The GaN was grown on SiO2 patterned substrates.
Romano, et al. (L. T. Romano, B. S. Krusor, and R. J. Molnar, Appl. Phys. Lett. 71 (1997) 2283) describes formation of GaN material with a defect density of 5xc3x97107 cmxe2x88x922 at the upper surface of the material and discloses that xe2x80x9cmany of the threading dislocations are not perpendicular to the surface; therefore, dislocation reactions can occur with increasing film thickness.xe2x80x9d
Thus, the art generally has taught away from the process conditions for growth of (Ga, Al, In)nitride materials that are employed in the practice of the present invention. The art also has not achieved a dislocation density less than 107 cmxe2x88x922 for crack-free areas larger than 1 cm2.
The art teaches the use of a two step growth process for the growth of GaN-based materials. Relative to the two step process of the present invention hereinafter more fully described, the first step in prior art processes is, however, carried out at substantially lower temperature (400-600xc2x0 C.), the first step growth layer is much thinner ( less than 200 nm in all cases), and the role of the first step in such prior art processes is to promote uniform surface coverage or nucleation on the substrate. Defect density less than 108 cmxe2x88x922 have not been achieved using this method. The first layer in the prior art processes is amorphous or highly defective.
U.S. Pat. No. 5,563,422 issued Oct. 8, 1996 to S. Nakamura et al. describes a gallium nitride-based III-V compound semiconductor device having a gallium nitride-based III-V compound semiconductor layer on a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The substrate may be sapphire or other electrically insulating substrate.
In the Nakamura et al. patent, the GaN layer provided on the substrate is formed by MOCVD. In practice of the teachings of the Nakamura et al. patent, the GaN nucleation layer thickness achievable is only on the order of 100 xc3x85. The defect density in the nucleation layers is thought to be high, perhaps on the order of 1E11 cmxe2x88x922 or greater, and yields a defect density of 1E9 to 1E10 cmxe2x88x922 or greater in the subsequently grown GaN layer.
U.S. Pat. No. 5,385,562 issued Jan. 31, 1995 to T. D. Moustakas describes a method of preparing highly insulating GaN single crystal films by MBE by a two step growth process that includes a low temperature nucleation step and a high temperature growth step. The low temperature nucleation process is carried out at 100-400xc2x0 C., resulting in an amorphous GaN nucleation layer of thickness between 200 and 500 xc3x85. The defect density in the nucleation layer is 1E11 cmxe2x88x922 or greater, and yields a defect density of 1E9 to 1E10 cmxe2x88x922 or greater in the subsequently grown GaN layer.
Japanese Patent 60-256806 to Akasaki et al. describes an AlN nucleation step, grown at 600xc2x0 C. to thicknesses of approximately 50 nm by MOCVD. Similarly, the defect density in the nucleation layer is thought to be high, e.g., 1E11 cmxe2x88x922 or greater, and yields a defect density of 1E9 to 1E10 cmxe2x88x922 or greater in the subsequently grown GaN layer.
It would be a substantial advance in the art to utilize substrates such as sapphire, on which (Ga,Al,In)N could be reliably and reproducibly grown with a substantially reduced defect density, as compared for example to the defect levels which are typically achieved by growth of epitaxial layers of GaN on sapphire, by molecular beam epitaxy (MBE), metal-organic vapor phase epitaxy (MOVPE), and prior art hydride vapor phase epitaxy (HVPE).
It therefore is an object of the present invention to provide a low defect density (Ga,Al,In)N material and a process for making same.
It is another object of the invention to provide a low defect density, substantially crack-free (Ga, Al, In)N material which is homogeneous over a large area.
It is still another object of the invention to provide (Ga,Al,In)N material on lattice-mismatched materials such as sapphire, which has a substantially reduced level of defects relative to (Ga,Al,In)N produced by the prior art.
It is another object of the invention to provide a low defect density, large area, substantially crack-free (Ga,Al,In)N material on lattice mismatched materials which are removable to enable low defect density, large area, substantially crack-free, free-standing (Ga,Al,In)N material.
It is yet another object of the present invention to provide (Ga, Al, In)N material on lattice-mismatched materials such as sapphire, with or without buffer layers, surface preparation, nucleation layers, or other intermediate layers between the substrate and the (Ga,Al,In)N material.
It is another object of the invention to provide a two-stage growth technique that overcomes the deficiencies of the prior art.
Other objects and advantages will be more fully apparent from the ensuing disclosure and appended claims.
The present invention relates to a low defect density, substantially crack-free (Ga,Al,In)N material, useful for fabrication of Group III-V nitride devices, and also relates to a vapor phase epitaxy process for making such low defect density, substantially crack-free (Ga,Al,In)N material.
In one aspect, the invention relates to a low defect density, large area, substantially crack-free (Ga, Al, In)N material. Such material may be of a free-standing type, or alternatively may be supported on a lattice-mismatched template material.
In another aspect, the present invention relates to a low defect density (Ga, Al, In)N material, formed on a substrate compatible therewith, in which defects of the (Ga, Al, In)N material are predominantly threading dislocations (TDs) that are angled with respect to the growth direction. In a specific embodiment, wherein the (Ga,Al,In)N material is GaN and the substrate comprises (0001) sapphire, the TDs are angled with respect to the [0001] growth direction.
In another aspect, the invention relates to a low defect density, substantially crack-free (Ga,Al,In)N material, which is homogeneous over large area, wherein the x,y dimensions preferably exceed 10 mm, and more preferably exceed 20 mm and most preferably exceed 40 mm.
In another aspect, the invention relates to a low defect density (Ga, Al, In)N material, formed on a substrate compatible therewith, in which defects of the (Ga, Al, In)N material are predominantly threading dislocations (TDs) that are angled with respect to the growth direction, as measured with respect to (Ga, Al, In)N growth on (0001) sapphire in the  less than 0001 greater than  direction, wherein at least 10% of such dislocations have a tilt angle that is in the range of from about 0.1 to about 40xc2x0, more preferably with at least 40% of the dislocations having a tilt angle in the range of from about 0.1 to about 40xc2x0, and most preferably with at least 70% of the dislocations having a tilt angle in the range of from about 0.1 to about 40xc2x0.
As used in such context, the tilt angle is the included angle between the growth direction of the (Ga, Al, In)N being formed on the substrate and the line defined by a linear segment of a single threading dislocation in such material.
In another aspect, the present invention relates to a low defect density (Ga, Al, In)N material, formed on a substrate compatible therewith, in which defects of the (Ga, Al, In)N material are predominantly mixed type threading dislocations (TDs). In a specific embodiment, wherein the (Ga, Al, In)N m material is GaN and the substrate comprises (0001) sapphire, the Burgers vectors lie along either of +/xe2x88x92[1,0,xe2x88x921,1], +/xe2x88x92[0,1,xe2x88x921,1] or +/xe2x88x92[1,1,xe2x88x922,1].
In another aspect, the present invention relates to a low defect density (Ga, Al, In)N material, formed on a substrate compatible therewith, in which defects of the (Ga, Al, In)N material are predominantly mixed type threading dislocations (TDs), wherein at least 60% of all threading dislocations have mixed character, more preferably at least 75% of all threading dislocations have mixed character, and most preferably at least 90% of all threading dislocations have mixed character.
In another aspect, the present invention relates to a substantially crack-free (Ga, Al, In)N material which enables the deposition or placement thereon of subsequent substantially crack-free (Ga,Al,In)N layers.
The substrate for the (Ga, Al, In)N material may comprise sapphire, silicon, silicon carbide, diamond, lithium gallate, lithium aluminate, zinc oxide, spinel, magnesium oxide, gallium arsenide, silicon-on-insulator, carbonized silicon-on-insulator, gallium nitride, etc., including conductive as well as insulating and semi-insulating substrates, twist-bonded substrates, compliant substrates, etc.
The low defect density material may be of significant thickness, e.g., greater than 100 micrometers in thickness (in the growth direction). The low defect density material has a defect density, measured on sapphire as a reference material, that is less than about 107 defects/cm2 at the upper surface of the material, and more preferably less than about 106 defects/cm2 at the upper surface of the material. Such defect densities are described as a number of threading dislocations per unit area at an upper surface of the material.
In a further aspect, the present invention relates to a method of forming such a low defect density material, by growing a (Ga, Al, In) N film on a compatible substrate by VPE at what have been traditionally viewed by the prior art as xe2x80x9csub-optimumxe2x80x9d growth conditions for sufficient time and under sufficient growth conditions yielding a substantially crack free (Ga, Al, In) N film in which the defects are predominantly threading dislocations that are angled with respect to the growth direction.
For example, in any given set of process conditions for growing a (Ga, Al, In) N film, a process variable may be selectively varied to determine the xe2x80x9ctraditional optimalxe2x80x9d process condition for that variable, at which the optimum surface morphology, crystallinity and defect density are obtained for thinner growth layers (less than 10 microns). Illustrative of such process variable are growth temperature, ratio of precursors for vapor-phase film formation, growth pressure and growth rate.
Once the traditional optimal process conditions of the selected process variable are determined, for best surface morphology, crystallinity and defect density of thinner base layers, xe2x80x9clow surface mobilityxe2x80x9d process conditions for the selected variable, still in the vicinity of the traditional optimal value, can be determined, at which the defects in the vicinity of the film/substrate interface is a denser network of tangled defects (mixed defects) which transition with increasing film thickness to defects which are predominantly threading dislocations that are angled with respect to the growth direction. Such low surface mobility process conditions may thus be determined readily without undue experimentation by those of ordinary skill in the art, by selectively varying the HVPE process variable, and examining the defect structure and density in the resulting film material. Such process variables may for example include growth temperature and/or growth rate. The low surface mobility process condition may therefore include a lower growth temperature than the temperature that is utilized for traditional optimal growth, and/or a higher growth rate than the growth rate that is employed for traditional optimal growth. Other process conditions that may be alternatively or additionally employed to potential advantage in the practice of the invention are increased growth pressure conditions, and decreased V/III ratio of reactants for the growth process.
The substrate upon which the (Ga,Al,In)N material is deposited can be tailored to enhance the properties of the (Ga, Al, In) N material. The substrate material can be chosen so that it can be easily removed in situ or ex situ, to yield the (Ga, Al, In) N material as a free-standing film, by a process as described in co-pending U.S. patent application Ser. No. 08/955,168 filed Oct. 21, 1997 in the names of Michael A. Tischler, Thomas F. Kuech and Robert P. Vaudo for xe2x80x9cBulk Single Crystal Gallium Nitride and Method of Making the Same,xe2x80x9d and U.S. Pat. No. 5,679,152 issued Oct. 21, 1997; U.S. application Ser. No. 08/984,473 filed Dec. 3, 1997; U.S. provisional patent application No. 60/031,555 filed Dec. 3, 1996 in the names of Robert P. Vaudo, Joan M. Redwing, Michael A. Tischler and Duncan W. Brown, the disclosures of which are hereby incorporated herein by reference in their entireties.
The substrate material can also be separated from the (Ga,Al,In)N and/or chemically and/or mechanically removed from the (Ga,Al,In)N material.
The HVPE growth process used to form the (Ga, Al, In) N material in the method of the present invention may be carried out by reacting a vapor-phase (Ga, Al, In) chloride with a vapor-phase nitrogenous compound in the presence of the substrate, to grow the (Ga, Al, In) nitride layer on the substrate.
The nitrogen-containing compound may be any suitable compound, such as ammonia, hydrazine, azides, nitrites, amines, polyamines, etc.
The vapor-phase III-chloride advantageously is formed by contacting vapor-phase hydrogen chloride with molten (Ga, Al, In) to yield the vapor-phase (Ga, Al, In) chloride. The molten (Ga, Al, In) desirably is of very high purity, preferably having a purity of at least xe2x80x9c5-9sxe2x80x9d (i.e., 99.99999+%), and more preferably having a purity of at least xe2x80x9c7-9sxe2x80x9d (i.e., 99.9999999+%), as determined on a weight percentage basis of the total weight of the source metal material.
The (Ga, Al, In)N material grown by the aforementioned method may be grown at relatively high rate, e.g., at a growth rate of at least 10 xcexcm/hour, more preferably of at least 50 xcexcm/hour, and most preferably of at least 100 xcexcm/hour, to produce a (Ga, Al, In)N material with a low threading dislocation defect density, e.g., less than 108 threading dislocation defects/cm2, more preferably less than 107 threading dislocation defects/cm2, and most preferably less than 106 threading dislocation defects/cm2.
In a specific method aspect, the invention relates to a method of forming a (Ga, Al, In)N material, comprising depositing a (Ga, Al, In)N material layer on a substrate or base structure by a HVPE growth process involving reaction of (Ga, Al, In), hydrogen chloride and ammonia, and conducted at a temperature of from about 985xc2x0 C. to about 1010xc2x0 C., at a growth rate of from about 50 to about 150 micrometers per hour, at a pressure of from about 10 to about 800 torr, and at a molar ratio of ammonia to hydrogen chloride of from about 20 to about 40.
The (Ga, Al, In)N material grown by the method of the invention may be used as a substrate for fabrication thereon of a microelectronic device or a device precursor structure, by a process including deposition of device layers by a suitable deposition technique, e.g., metalorganic chemical vapor deposition (MOCVD), molecular-beam epitaxy (MBE), etc.
The invention relates in another aspect to a microelectronic device or device precursor structure including a layer of the (Ga, Al, In)N material of the present invention. Such device or precursor structure may be an optical, electrical, optoelectronic, or other device, e.g., a device selected from laser diodes, LEDs, detectors, bipolar transistors, Schottky diode, permeable base transistors, high electron mobility transistors (HEMTs), vertical MISFETs, etc.
Other aspects and features of the invention will be more fully apparent from the ensuing disclosure.